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the information in this document is subject to change without notice. description the m pd78324 is a 16/8-bit single-chip microcontroller that incorporates a high-performance 16-bit cpu. the m pd78324 is one of 78k/iii series. the internal capacity is significantly increased compared with the conventional m pd78322. a realtime pulse unit for realtime pulse control required in motor control, an a/d converter, a rom, and a ram have been integrated into one chip. the m pd78324 incorporates 32k-byte mask rom and 1024-byte ram. the m pd78323 is a rom-less version of the m pd78324. also, it is provided the m pd78p324 as an on-chip prom product. detailed information about product features and specifications can be found in the following document. m pd78322 users manual : ieu-1248 features internal 16-bit architecture and external 8-bit data bus high-speed processing by pipeline control and instruction prefetch ? minimum instruction execution time: 250 ns (with 16 mhz external clock in operation) instruction set suitable for control operations ( m pd78312 upward compatible) ? multiply/divide instructions (16 bits 16 bits, 32 bits ? 16 bits) ? bit manipulation instruction ? string instruction, etc. on-chip high-function interrupt controller ? 3-level priority specifiable ? 3-type interrupt processing mode selectable (vectored interrupt function, context switching function, and macro service function) variety of peripheral hardware ? realtime pulse unit ? 8-channel, 10-bit a/d converter ? watchdog timer powerful serial interface (with an on-chip dedicated baud rate generator) ? uart 1 channel ? sbi (nec standard serial bus interface) ? 3-wire serial i/o applications motor control devices unless there are any particular diferences, the m pd78324 is described as the representative model in this document. 1991 data sheet m pd78323,78324 mos integrated circuit 16/8-bit single-chip microcontroller 1 channel the mark shows major revised points. document no. u10456ej4v0ds00 (4th edition) (previous no. ic-2870) date published november 1995 p printed in japan
m pd78323, 78324 2 ordering information part number package on-chip rom m pd78323gj-5bj 74-pin plastic qfp (20 20 mm) none m pd78323lp 68-pin plastic qfj ( 950 mil) none m pd78324gj- -5bj 74-pin plastic qfp (20 20 mm) mask rom m pd78324lp- 68-pin plastic qfj ( 950 mil) mask rom remark indicates rom code number.
3 m pd78323, 78324 pin configuration 74-pin plastic qfp (20 20 mm) m pd78323gj-5bj m pd78324gj- -5bj 74 p42/ad2 73 p41/ad1 72 p40/ad0 71 astb 70 p90/rd 69 p91/wr 68 p92/tas 67 p93/tmd 66 v ss 65 ea 64 p07/rtp7 63 p06/rtp6 62 p05/rtp5 61 p04/rtp4 60 p03/rtp3 59 p02/rtp2 58 p01/rtp1 57 nc 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 p00/rtp0 wdto v ss nc x1 x2 reset p85/to11 p84/to10 p83/to03 p82/to02 p81/to01 p80/to00 nc p34/sck p33/si/sb1 p32/so/sb0 p31/r x d p30/t x d p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 nc p56/a14 p57/a15 v dd av ss p70/an0 p71/an1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6 p77/an7 av ref av dd v dd p20/nmi p21/intp0 p22/intp1 p23/intp2 p24/intp3 p25/intp4 p26/intp5 p27/intp6/ti nc nc caution the nc pin should be connected to vss for noise control (can also be left open).
m pd78323, 78324 4 ? 68-pin plastic qfj ( 950 mil) m pd78323lp m pd78324lp- 9 p27/intp6/ti 8 p26/intp5 7 p25/intp4 6 p24/intp3 5 p23/intp2 4 p22/intp1 3 p21/intp0 2 p20/nmi 1 v ss 68 av dd 67 av ref 66 p77/an7 65 p76/an6 64 p75/an5 63 p74/an4 62 p73/an3 61 p72/an2 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 p30/t x d p31/r x d p32/so/sb0 p33/si/sb1 p34/sck p80/to00 p81/to01 p82/to02 p83/to03 p84/to10 p85/to11 reset x2 x1 v ss wdto rtp0/p00 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 rtp1/p01 rtp2/p02 rtp3/p03 rtp4/p04 rtp5/p05 rtp6/p06 rtp7/p07 ea v ss p93/tmd p92/tas p91/wr p90/rd astb p40/ad0 p41/ad1 p42/ad2 p71/an1 p70/an0 av ss v dd p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
5 m pd78323, 78324 p00 to p07 : port0 reset : reset p20 to p27 : port2 x1, x2 : crystal p30 to p34 : port3 wdto : watchdog timer output p40 to p47 : port4 ea : external access p50 to p57 : port5 tmd : turbo mode p70 to p77 : port7 tas : turbo access strobe p80 to p85 : port8 wr : write strobe p90 to p93 : port9 rd : read strobe nmi : nonmaskable interrupt astb : address strobe intp0 to intp6 : interrupt from peripherals ad0 to ad7 : address/data bus rtp0 to rtp7 : realtime port a8 to a15 : address bus ti : timer input an0 to an7 : analog input t x d : transmit data av ref : analog reference voltage r x d : receive data av ss : analog v ss sb0/so : serial bus/serial output av dd : analog v dd sb1/si : serial bus/serial input v dd : power supply sck : serial clock v ss : ground to00 to to03 : nc : non-connection to10 to to11 : timer output
m pd78323, 78324 6 general description of functions ? rom : 32k bytes ( m pd78324) none ( m pd78323) ? ram : 1k bytes 64k bytes 8 bits 16 8 banks (memory mapping) ? input port : 16 (dual-function as analog input: 8) ? input/output port : 39 ( m pd78324) 21 ( m pd78323) ? 18/16-bit free running timer 1 ? 16-bit timer/event counter 1 ? 16-bit compare register 6 ? 18-bit capture register 4 ? 18-bit capture/compare register 2 ? realtime output port 8 serial interface with a dedicated baud rate generator ? uart : 1 channel ? sbi (nec serial bus interface) : 1 channel 10-bit resolution (8 analog inputs) ? external : 8, internal : 14 (dual-function as external : 2) ? 3 processing modes (vectored interrupt function, context switching function, and macro service function) internal : 1 stop mode/halt mode 16-bit transfer/operation instruction, multiplication/division instruction (16 16, 32 16), bit manipu- lation instruction, string instruction, etc. on-chip watchdog timer ? 68-pin plastic qfj ( 950 mil) ? 74-pin plastic qfp (20 20 mm) basic instructions minimum instruction execution time memory space general registers a/d converter interrupt test factor standby instruction set others package 250 ns (with 16 mhz external clock in operation) internal memory i/o line real-time pulse unit serial communication interface 111
7 m pd78323, 78324 differences between m pd78324 and 78323 internal rom input input /output port 4 (p40 to p47) port 5 (p50 to p57) port 9 (p90 to p93) memory expansion mode register (mm) port 5 mode register (pm5) item i/o line product name always p90 and p91 function as rd strobe and wr strobe signal output, respectively. port 4 i/o mode is set as an 8-bit unit . port 5 i/o mode is set bit-wise. note maintenance product m pd78324 m pd78323 32k bytes none 16 (dual-function as analog input: 8) 39 21 specifiable as i/o as an 8-bit unit. functions as multiplexed address/data buses functions always as multiplexed address/data (ad0 to ad7) in the external memory expansion buses. mode. specifiable as i/o bit-wise. functions as address bus (a8 to a15) in the functions always as address bus. external memory expansion mode. specifiable as i/o bit-wise. in the external memory expansion mode, p90 and p91 function as rd strobe signal output and wr strobe signal output, respectively. in the external memory high-speed fetch mode, p92 p93 function as tas output and tmd out- put respectively. in the m pd78324 emulation mode, turbo acces acces manager ( m pd71p301) note pa and pb pins are controlled as port 4 and port 5 emulation pins.
m pd78323, 78324 8 bcu rom/ram system control & bus control & prefetch control rom note 32k bytes peripheral ram 768 bytes exu alu general registers 128 bytes & data memory 128 bytes micro sequence control micro rom. main ram programmable interrupt controller timer/counter unit (realtime pulse unit) serial interface (sbi) (uart) (p20) nmi intp0?ntp5 (p21?26) (p80) to00 (p81) to01 (p82) to02 (p83) to03 (p84) to10 (p85) to11 (p27) ti/intp6 (p34) sck (p32) so/sb0 (p33) si/sb1 (p30) t x d (p31) r x d an0?n7 (p70?77) av dd av ss av ref wdto wdt a/d converter (10 bit) port p90?93 p80?85 p70?77 p50?57 p40?47 p30?34 p20?27 p00?07 (realtime port) v dd v ss ad0?d7 (p40?47) a8?15 (p50?57) ea tmd (p93) tas (p92) wr (p91) rd (p90) astb reset x2 x1 block diagram note the m pd78323 does not incorporate rom.
9 m pd78323, 78324 contents 1. list of pin functions ..................................................................................................................... 11 1.1 port pins ............................................................................................................................... ....................... 11 1.2 pins other than ports .......................................................................................................................... 12 1.3 pin input/output circuits and recommended connection of unused pins ................... 14 2. cpu architecture ............................................................................................................................ 16 2.1 memory space ............................................................................................................................... ............. 16 2.2 processor registers ............................................................................................................................ 19 2.2.1 control registers ........................................................................................................................... 20 2.2.2 general registers ........................................................................................................................... 22 2.2.3 special function registers (sfr) ................................................................................................ 24 2.3 data memory addressing ..................................................................................................................... 29 2.3.1 general register addressing ....................................................................................................... 29 2.3.2 short direct addressing ................................................................................................................ 29 2.3.3 special function register (sfr) addressing ............................................................................ 29 3. block functions .............................................................................................................................. 3 0 3.1 bus control unit (bcu) .......................................................................................................................... 30 3.2 execution unit (exu) ............................................................................................................................... .30 3.3 rom/ram ............................................................................................................................... ......................... 30 3.4 interrupt controller .......................................................................................................................... 30 3.5 port functions ............................................................................................................................... .......... 31 3.6 clock generator ............................................................................................................................... ..... 32 3.7 realtime pulse unit (rpu) ..................................................................................................................... 34 3.7.1 configuration ............................................................................................................................... ... 34 3.7.2 realtime output function ............................................................................................................. 36 3.8 a/d converter ............................................................................................................................... ............ 37 3.9 serial interface ............................................................................................................................... ....... 37 3.10 watchdog timer ............................................................................................................................... ........ 40 4. interrupt functions ...................................................................................................................... 41 4.1 overview ............................................................................................................................... ....................... 41 4.2 macro service ............................................................................................................................... ............ 42 4.3 context switching function .............................................................................................................. 44 4.3.1 context switching function at interrupt request ..................................................................... 44 4.3.2 context switching function by brkcs instruction ................................................................. 45 5. standby functions ......................................................................................................................... 46 6. external device expansion function .................................................................................... 47 7. operation after reset ................................................................................................................. 48 8. instruction set ............................................................................................................................... .49 9. electrical specifications .......................................................................................................... 63
m pd78323, 78324 10 10. package drawings .......................................................................................................................... 74 11. recommended soldering conditions ..................................................................................... 76 appendix a. list of 78k/iii series products ................................................................................ 77 appendix b. tools ............................................................................................................................... ..... 79 b.1 development tools ............................................................................................................................... .79 b.2 evaluation tools ............................................................................................................................... ..... 83 b.3 embedded software ............................................................................................................................... .83
11 m pd78323, 78324 1. list of pin functions 1.1 port pins dual- function pin rtp0 to rtp7 nmi intp0 intp1 intp2 intp3 intp4 intp5 intp6/ti t x d r x d so/sb0 si/sb1 sck ad0 to ad7 a8 to a15 an0 to an7 to00 to01 to02 to03 to10 to11 rd wr tas tmd p00 to p07 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p40 to p47 p50 to p57 p70 to p77 function pin name i/o port 0 8-bit input/output port input/output can be specified bit-wise also serves as a realtime output port. input input/ output port 4 8-bit input/output port input/output can be specified in 8-bit unit. port 5 8-bit input/output port input/output can be specified bit-wise port 7 dedicated port for 8-bit input port 8 6-bit input/output port input/output can be specified bit-wise input/ output input/ output input/ output input p80 p81 p82 p83 p84 p85 p90 p91 p92 p93 input/ output port 2 dedicated port for 8-bit input port 3 5-bit input/output port input/output can be specified bit-wise port 9 4-bit input/output port input/output can be specified bit-wise input/ output
12 m pd78323, 78324 rtp0 to rtp7 nmi intp0 intp1 intp2 intp3 intp4 intp5 intp6 ti t x d r x d so si sb0 sb1 sck ad0 to ad7 1.2 pins other than ports (1/2) a8 to a15 to00 to01 to02 to03 to10 to11 rd wr tas tmd wdto astb serial data output of asynchronous serial interface (uart) serial data input of asynchronous serial interface (uart) serial data output of clock synchronous serial interface in 3-wire mode serial data input of clock synchronous serial interface in 3-wire mode serial data output of clock synchronous serial interface in sbi mode dual- function pin function pin name i/o realtime output port which generates pulses in synchronization with the trigger signal transmitted from the realtime pulse unit (rpu). nonmaskable interrupot request input capable of specifying the effective at the rising or falling edge by a mode register. input output p00 to p07 p20 p21 p22 p23 p24 p25 p26 p27/ti p27/intp6 p30 p31 p32/sb0 p33/sb1 p32/so p33/si p34 p40 to p47 p50 to p57 p80 p81 p82 p83 p84 p85 p90 p91 p92 p93 CC CC input input external count clock input to timer 1 (tm1) output input output input /output input /output input /output output output output strobe signal output generated for external memory read operation strobe signal output generated for external memory write operation control signal output generated for access to turbo access manager m pd71p301 note signal output indicating that the watchdog timer has generated a nonmascable interrupt. timing signal output generated for externally latching the address information output from pins ad0 to ad7 in order to access the external memory. output output external interrupt request input capable of specifying the effective edgy by a mode register. input serial clock input/output of clock synchronous serial interface multiplexed address/data bus for external memory expansion address bus for external memory expansion pulse output from the realtime pulse unit note maintenance product
13 m pd78323, 78324 1.2 pins other than ports (2/2) dual- function pin function pin name i/o an0 to an7 av ref av dd av ss reset x1 x2 v dd v ss nc input input input input CC a/d converter analog input. a/d converter reference voltage input. a/d converter analog power supply a/d converter gnd system reset input crystal connect pin for sysem clock oscillation. when an external clock is supplied, the clock is input to x1 and the inverted clock is input to x2. (x2 can also be left open.) positive power supply gnd pin not internally connected. connected to v ss (gnd) (can also be left open). ea input in the m pd78324, ea pin is normally connected to v dd . connecting ea pin to v ss sets the rom-less mode and accesses the external memory. in the m pd78323, this pin should be fixed to 0 (low level). the ea pin level cannot be changed during operation.
14 m pd78323, 78324 1.3 pin input/output circuits and recommended connection of unused pins the pin input/output circuits, partly simplified, are shown in table 1-1 and figure 1-1. table 1-1. i/o circuit types of pins and their recommended connection methods when unused recommended connection method input/output circuit type pin p00/rtp0 to p07/rtp7 p20/nmi p21/intp0 to p26/intp5 p27/intp6/ti p30/t x d p31/r x d p32/so/sb0 p33/si/sb1 p34/sck p40/ad0 to p47/ad7 p50/a8 to p57/a15 p70/an0 to p77/an7 p80/to00 to p83/to03 p84/to10, p85/to11 p90/rd p91/wr p92/tas p93/tmd wdto astb ea reset av ref , av ss av dd nc input mode : individually connected to v dd or v ss via resistor output mode: leave open connected to v ss 5 2 5 8 5 9 5 5 3 4 1 2 CC CC CC input mode : individually connected to v dd or v ss via resistor output mode: leave open connected to v ss input mode : individually connected to v dd or v ss via resistor output mode: leave open leav open CC CC connected to v ss connected to v dd connected to v ss (can also be left open)
15 m pd78323, 78324 figure 1-1. pin input/output circuits type 1 type 2 type 5 type 8 type 3 type 4 type 9 p-ch n-ch in v dd in schmitt-trigger input having hysteresis characteristics. push-pull output which can become high-impedance output (with both p-ch and n-ch set to off) v dd out p-ch n-ch v dd out p-ch n-ch data output disable data output disable input enable in/out p-ch n-ch v dd v ref p-ch n-ch in comparator + (threshold voltage) input enable in/out p-ch n-ch v dd data output disable
16 m pd78323, 78324 2. cpu architecture 2.1 memory space in the m pd78324 a maximum of 64k bytes of memory can be addressed (see figure 2-1 ). program fetches can be performed within the area from 0000h to fdffh. however, when external memory expansion is implemented in the area from fe00h to ffffh (main ram and special function register area), program fetches can also be performed on this area. in this case, a program fetch is performed on the external memory, not on the main ram or special function registers. (1) vector table area interrupt request from the peripheral hardware, reset input, external interrupt request and interrupt branch address by break instruction are stored in the 0000h to 003fh 64-byte area. generation of an interrupt request sets the even address content of each table in the lower 8 bits of the program counter (pc) and the odd address content in the higher 8 bits. interrupt source vector table address reset (reset pin input) ........................................... 0000h nmi (nmi pin input) ................................................ 0002h wdt (watchdog timer) ............................................ 0004h tmf0 (realtime pulse unit) ....................................... 0006h exf0 (intp0 pin input) ............................................. 0008h exf1 (intp1 pin input) ............................................. 000ah exf2 (intp2 pin input) ............................................. 000ch exf3 (intp3 pin input) ............................................. 000eh exf4/ccfx0 (intp4 pin input/realtime pulse unit) ............. 0010h exf5/ccfx1 (intp5 pin input/realtime pulse unit) ............. 0012h exf6/ti (intp6/ti pin input) ........................................ 0014h cmf00 (realtime pulse unit) ....................................... 0016h cmf01 (realtime pulse unit) ....................................... 0018h cmf02 (realtime pulse unit) ....................................... 001ah cmf03 (realtime pulse unit) ....................................... 001ch cmf10 (realtime pulse unit) ....................................... 001eh cmf11 (realtime pulse unit) ....................................... 0020h srf (serial receive complete) ................................ 0024h stf (serial send complete) .................................... 0026h csiif (clock synchronous serial interface) .............. 0028h adf (a/d converter) ................................................ 002ah operation code trap ................................................................... 003ch brk (break instruction) ........................................... 003eh if bit 1 (tpf) of cpu control word (ccw) is set to 1, the 8002h to 803fh external memory area is used as an interrupt vector table in place of 0002h to 003fh.
17 m pd78323, 78324 note maintenance product (2) callt table area 32 tables of call addresses of 1-byte call instruction (callt) can be stored in the 0040h to 007fh 64-byte area. if bit 1 (tpf) of cpu control word (ccw) is set to 1, the 8040h to 807fh external memory area is used as a callt instruction table in place of 0040h to 007fh. (3) callf entry area the 0800h to 0fffh area can be directly subroutine-called by 2-byte call instruction (callf). (4) on-chip ram area a 1024-byte ram is built in fb00h to feffh. this area is composed of the following 2 rams. ? peripheral ram : fb00h to fdffh (768 bytes) ? main ram : fe00h to feffh (256 bytes) the main ram can be accessed at high speed. in the main ram area, the macro service control word and general register group composed of 8 register banks are mapped onto the 36 bytes from fe06h to fe2bh and the 128 bytes from fe80h to feffh, respectively. (5) special function register (sfr) area registers having specially assigned functions, such as on-chip peripheral hardware mode registers and control registers, are mapped in the ff00h to ffffh area. addresses without mapped registers cannot be accessed. (6) external memory area the m pd78324 can add external memories (rom, ram) to the 32k-byte (8000h to ffffh) area. the m pd78323 can connect external memories (rom, ram) to the 64k-byte (0000h to ffffh) area. each external memory can be accessed using p40/ad0 to p47/ad7 (multiplexed address/data bus), p50/a8 to p57/a15 (address bus) and rd, wr and astb signals. the external access area is mapped in the ffd0h to ffdfh 16-byte area of the special function register (sfr). in this way, the external memory can be accessed by sfr addressing. dedicated pins (tas and tmd pins) are provided to connect turbo access manager ( m pd71p301) note . if the m pd71p301 is used, the program processing speed equal to that of the on-chip rom can be obtained.
18 m pd78323, 78324 callf instruction entry area (2048 8) special function register (sfr) (256 8) main ram (256 8) external memory note (31488 8) internal rom (32768 8) ffffh ff00h feffh fb00h faffh 8000h 7fffh 0000h program memory data memory program memory data memory data memory memory space (64k 8) general register (128 8) macro service control (36 8) data area (1024 8) program area callf instruction table area (64 8) program area vector table area (64 8) feffh fe80h fe06h fb00h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 7fffh fe2bh external memory (64256 8) ea = h ( pd78324) ea = l ? pd78323 ? pd78324 rom-less mode 0fffh 0000h m m m peripheral ram (768 8) fe00h fdffh figure 2-1. memory map note accessed in external memory expansion mode. caution for word access (including stack operations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value.
19 m pd78323, 78324 2.2 processor registers the processor registers consist mainly of three groups. they are general registers consisting of 8 banks of sixteen 8- bit registers, control registers consisting of one 8-bit register and three 16-bit registers, and special function registers su ch as peripheral hardware i/o mode registers. figure 2-2. register configuration remark the ccws of the control registers are mapped in the special function register (sfr) area. psw s p p c ccw r1 r3 r5 r7 r9 r11 r13 r15 r0 r2 r4 r6 r8 r10 r12 r14 sfr 255 7 sfr 253 sfr 251 sfr 249 sfr 1 sfr 254 sfr 252 sfr 250 sfr 248 sfr 0 07 0 7070 70 15 0 control registers general registers special function registers
20 m pd78323, 78324 2.2.1 control register the control registers carry out dedicated functions such as control of the program sequence, status and stack memory, and modification of operand addressing. they consist of three 16-bit registers and one 8-bit register. (1) program counter (pc) this is a 16-bit register which holds the address information of the next program to be executed. it is normally incremented according to the number of bytes of the instruction to be fetched. if an instruction with data branch is executed, immediate data and the register content are set. reset input sets and branches the data of 0000h and 0001h reset vector tables in the pc. (2) program status word (psw) this is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. read/ write access is carried out in units of the higher 8 bits (pswh) or lower 8 bits (pswl). each flag can be operated using the bit operation instruction. if an interrupt request is made or brk instruction is executed, data is automatically saved in the stack and is recovered by reti or retb instruction. all bits are reset to 0 by reset input. figure 2-3. psw format (a) interrupt priority level transition flag (lt) 76543210 uf rbs2 rbs1 rbs0 0 0 0 0 76543210 s z rss ac ie p/v lt cy this flag is used to control the interrupt priority. for normal operation of the interrupt control circuit, this bit must not be operated by a program. (b) carry flag (cy) if a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated into bit 7 or 15, this flag is set to 1. in all other cases, this flag is reset to 0. this flag can be tested by the conditiona l branch instruction. when a bit control instruction is executed, this flag functions as a bit accumulator. (c) zero flag (z) when the operation result is zero, this flag is set to 1. in all other cases, this flag is reset to 0. this flag can be tested by the conditional branch instruction. (d) sign flag (s) when msb of the operation result is 1, this flag is set to 1. when the msb is 0, this flag is reset to 0. this flag can be tested by the conditional branch instruction. (e) parity/overflow flag (p/v) only when an overflow or underflow occurs as twos complement during execution of an arithmetic operation instruction, this flag is set to 1. in all other cases, it is reset to 0 (overflow flag operation). if the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag is set to 1. if the bit number is odd, this flag is reset to 0 (parity flag operation). this flag can be tested by the conditional branch instruction. pswh pswl
21 m pd78323, 78324 (f) auxiliary carry flag (ac) if a carry is generated out of bit 3 as a result of operation or a borrow is generated into bit 3, this flag is set to 1. in all other cases, this flag is reset to 0. this flag can be tested by the conditional branch instruction. (g) register set select flag (rss) this flag is used to specify general registers x, a, c and b. as shown in table 2-1, the rss value determines the relationship between the functional register and the absolute register. thus, another register set (x, a, c, b) can be used by switching the rss flag. (h) interrupt request enable flag (ie) this flag is used to indicate interrupt request enable/disable. this flag is set to 1 by execution of ei instruction and is reset to 0 byexecution of di instruction or acceptance of an interrupt. (i) register bank select flag (rbs0 to rbs2) this is a 3-bit flag to select one of eight register banks (rbank0 to rbank7). (j) user flag (uf) this flag is set or reset in the user program and can be used for program control. (3) stack pointer (sp) this is a 16-bit register which holds the first address of the stack area (lifo format) of the memory. it is operated by a dedicated instruction. sp is decremented before write (save) operation into the stack memory and is incremented after read (return) operation from the stack memory. since sp becomes indeterminate by reset input, it must be set before subroutine call.
22 m pd78323, 78324 (4) cpu control word (ccw) this is an 8-bit register consisting of cpu control related flags. it is mapped in the special function register area and can be controlled by the software. all bits are reset to 0 by reset input. figure 2-4. ccw format ? table position flag (tpf) this flag is used to specify the interrupt vector table area and the memory area used as callt instruction table area. as tpf has been reset to 0 after application of reset input, the 0000h to 007fh address is used as each table area. the 8002h to 807fh address of the external memory area in place of 0002h to 007fh address can be used as each table area by setting tpf to 1 using the software. the vector tables of the brk instruction, operation code trap interrupt and reset input are fixed to 003eh, 003ch and 0000h, respectively, and they are not affected by tpf. 2.2.2 general registers these are 128-byte registers mapped in the special area (fe80h to feffh) of the internal ram space. they consist of eight register banks. the general register in the bank consists of sixteen 8-bit registers. figure 2-5. general register memory location 76543210 000000tpf0 ccw (fh) rp7 (eh) (dh) rp6 (ch) (bh) rp5 (ah) (9h) rp4 (8h) (7h) rp3 (6h) (5h) rp2 (4h) (3h) rp1 (2h) (1h) rp0 (0h) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 70 70 15 0 rbnk0 rbnk1 rbnk2 rbnk3 rbnk4 rbnk5 rbnk6 rbnk7 feffh fe80h 8-bit processing 16-bit processing
23 m pd78323, 78324 the sixteen 8-bit registers can function as eight 16-bit register pairs (rp0 to rp7) as well. as shown in table 2-1, the sixteen 8-bit registers are characterized by functional names. the x register functions as the lower half of the 16-bit accumulator, the a register functions as the upper half of the 8-bit or 16-bit accumulator, the b and c registers function as a counter, and de, hl, vp and up function as address register pairs. in particular the vp register is function as a base register and the up register is as a user stack pointer. the unique function register charges as shown in table 2-1 according to the value of the register set select flag (rss) in the psw. thus, if the program is described by the functional name, another register set of x, a, c and b can be used by means of the rss flag. the m pd78324 can carry out processed data addressing operations, implied addressing by functional names with importance attached to the unique function of each register and register addressing by absolute names with a view to fast processing with a small number of data transfers or creating highly descriptive programs. table 2-1. general register configuration r5 a r6 c r7 b r8 vp l vp l r9 vp h vp h r10 up l up l r11 up h up h r12 e e r13 d d r14 l l r15 h h absolute functional name name rss = 0 rss = 1 r0 x r1 a r2 c r3 b r4 x rp5 up up rp6 de de rp7 hl hl absolute functional name name rss = 0 rss = 1 rp0 ax rp1 bc rp2 ax rp3 bc rp4 vp vp
24 m pd78323, 78324 2.2.3 special function registers (sfr) these registers are provided with special functions. they include various peripheral hardware mode registers and control registers (ccw). the special function registers are assigned in the ff00h to ffffh 256-byte space. short direct memory addressing is applied to the ff00h to ff1fh 32-byte area for processing with a short word length. the bit manipulation, arithmetic and transfer instructions can be executed in all areas. the ffd0h to ffdfh 16-byte area is externally accessible by sfr addressing. thus, the external memory can be accessed and the external device bit manipulation can be carried out by an instruction having a short word length. table 2-2 lists the special function registers (sfr). the items in the table have the following meanings. ? symbol................. indicates the address of the built-in special function register. can be described in the instruction operand column. ? r/w.......................indicates if the corresponding special function register can read or write. r/w : read/write enable r : read only enable (register bit test enable) w : write only enable ? manipulable bit unit ....................... indicates the applicable operation bit unit for the corresponding special function register. 16-bit manipulable sfr can be described in operand sfrp. when specified by an address, an even address is described. 1-bit manipulable sfr can be described by the bit operation instruction. ? on reset ...............indicates the state of each register when reset is input. cautions 1. addresses for which no special function registers have been assigned cannot be accessed in the ff00h to ffffh area. 2. do not write to the read only register. if data is written, the internal circuit may malfunction.
25 m pd78323, 78324 table 2-2. list of special function registers (1/4) ff00h ff02h ff03h ff04h ff05h ff07h ff08h ff09h ff0ah ff0bh ff10h ff11h ff12h ff13h ff14h ff15h ff16h ff17h ff18h ff19h ff1ah ff1bh ff20h ff23h ff25h ff28h ff29h ff2ah ff2bh ff2ch ff2dh ff30h ff31h ff32h ff33h ff34h ff35h l l l l CC l l l l l l l l l l l l l l CC l l l l l l l l l l CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC l l CC l l CC l l CC l l CC l l CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC port 0 port 2 port 3 port 4 port 5 port 7 port 8 port 9 free running counter (lower 16 bits) note capture register x0 (lower 16 bits) note capture register 01 (lower 16 bits) note capture register 02 (lower 16 bits) note capture register 03 (lower 16 bits) note capture/compoare register x0 (lower 16 bits) note capture/compoare register 01 (lower 16 bits) note port 0 mode register port 3 mode register port 5 mode register port 8 mode register port 9 mode register free runnting counter (higher 16 bits) note timer register 1 capture register x0 (higher 16 bits) note capture register 01 (higher 16 bits) note capture register 02 (higher 16 bits) note 1 bit 8 bits 16 bits address special function register (sfr) name r/w on reset symbol p0 p2 p3 p4 p5 p7 p8 p9 r/w r r/w r r/w r r/w w r tm0lw ctx0lw ct01lw ct02lw ct03lw ccx0lw cc01lw pm0 pm3 pm5 pm8 pm9 tm0uw tm1 ctx0uw ct01uw ct02uw undefined 0000h undefined ffh 1 1111b ffh 11 1111b 1111b 0000h undefined manipulable bit unit CC CC CC CC CC l l l l l l l l l l l l l l CC CC CC CC CC l l l l l l l l l l note upper or lower half of 18-bit register.
26 m pd78323, 78324 capture register 03 (higher 16 bits) note capture/compoare register x0 (higher 16 bits) note capture/compoare register 01 (higher 16 bits) note port 0 mode control register realtime output port reset register port 3 mode control register port 8 mode control register baud rate generator realtime output port register realtime output port reset register port read control register a/d converter mode register a/d conversion result register (for 16-bit access) a/d conversion result register (for upper 8-bit access) compare register 00 compare register 01 compare register 02 compare register 03 compare register 10 compare register 11 clock synchronous serial interface mode register serial bus interface control register serial i/o shift register CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC l l l l l l l l l l l l undefined 00h 0 0000b 00 0000b undefined 00h undefined 00h undefined l l l l l l CC CC CC CC l l CC CC CC CC l l CC l l l l l l l l l l l l CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC l l l l l l CC l l CC l l CC CC CC CC l l l l l l l l l l l l l l l l CC CC CC l l table 2-2. list of special function registers (2/4) ff36h ff37h ff38h ff39h ff3ah ff3bh ff40h ff41h ff43h ff48h ff4ch ff4dh ff60h ff61h ff62h ff68h 1 bit 8 bits 16 bits address special function register (sfr) name r/w on reset symbol manipulable bit unit ff6ah ff6bh ff70h ff71h ff72h ff73h ff74h ff75h ff76h ff77h ff7ch ff7dh ff7eh ff7fh ff80h ct03uw ccx0uw cc01uw pmc0 rtps pmc3 pmc8 brg rtp rtpr prdc adm adcr adcrh cm00 cm01 cm02 cm03 cm10 cm11 csim sbic sio r r/w w r/w w r/w r r/w r/w ff82h ff86h note upper or lower half of 18-bit register.
27 m pd78323, 78324 CC l l CC l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l CC CC l l l l l l l l l l l l CC CC l l l l l l l l l l l l CC CC l l l l l l l l l l l l CC CC rxb txs tmc brgm prm toc0 toc1 rpum stbc ccw wdm mm pwc fcc asynchronous serial interface mode register asynchronous serial interface status register serial receive buffer :uart serial send shift register :uart timer control register baud rate generator mode register prescalar mode register timer output control register 0 timer output control register 1 rpu mode register standby control register cpu control word watchdog timer mode register memory expansion mode register programmable weight control register fetch cycle control register external acces area interrupt request flag rgister 0l interrupt request flag rgister 0h interrupt request flag rgister 1l CC interrupt mask flag rgister 0l interrupt mask flag rgister 0h interrupt mask flag rgister 1l CC priority specify bufer register 0l priority specify bufer register 0h priority specify bufer register 1l CC interrupt processing mode specify register 0l interrupt processing mode specify register 0h interrupt processing mode specify register 1l CC table 2-2. list of special function registers (3/4) 1 bit 8 bits 16 bits address special function register (sfr) name r/w on reset symbol manipulable bit unit asim asis r/w r w r/w r/w note r/w r/w note r/w note write enable in case of special instructions. ff8ch ff8eh ffb0h ffb1h ffb2h ffb8h ffb9h ffbfh ffc0h ffc1h ffc2h ffc4h ffc6h ff88h ff8ah ffc9h ffd0h to ffdfh ffe0h ffe1h ffe2h ffe3h ffe4h ffe5h ffe6h ffe7h ffe8h ffe9h ffeah ffebh ffech ffedh ffeeh ffefh if0 if1 mk0 mk1 pb0 pb1 ism0 ism1 if0l if0h if1l CC mk0l mk0h mk1l CC pb0l pb0h pb1l CC ism0l ism0h ism1l CC l l l l l l l l CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC l l l l l l l l l l l l l l l l 80h 00h undefined 00h 0000 000b 00h 22h 00h undefined 00h CC ffh 111b CC 00h CC 00h CC
28 m pd78323, 78324 table 2-2. list of special function registers (4/4) fff0h fff1h fff2h fff3h fff4h fff5h fff8h fff9h l l l l l l l l l l l l CC CC l l l l l l l l CC l l l l l l context switching enable register 0l context switching enable register 0h context switching enable register 1l CC external interupt mode register 0 external interupt mode register 1 in-service priority register priority specify register 1 bit 8 bits 16 bits address special function register (sfr) name r/w on reset symbol manipulable bit unit intm0 intm1 ispr prsl cse0l cse0h cse1l CC cse0 cse1 l l l l CC CC CC CC 00h CC 00h r/w r r/w 2.3 data memory addressing in the m pd78324, the internal ram space (fb00h to feffh) and the special function register area (ff00h to ffffh) are mapped in the fb00h to ffffh area. in the fe20h to ff1fh space of the data memory, short direct addressing enables direct addressing by 1-byte data in an instruction word. figure 2-6. data memory addressing space note when ea = l, and with the m pd78323, this is external memory. caution for word access (including stack operations) to the main ram area (fe00h-feffh), the address that specifies the operand must be an even value. ffffh ff1fh ff00h feffh fe80h fe00h fb00h 7fffh 0000h special function register (sfr) main ram external memory general register internal rom note sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing paste indexed addressing paste indexed addressing (provided with displacement) fe20h peripheral ram fdffh
29 m pd78323, 78324 2.3.1 general register addressing the general registers consist of eight register banks, each consisting of sixteen 8-bit registers or eight 16-bit registers. general register addressing is carried out using the register specify field of 3 or 4 bits supplied from an instruction word, the register bank select flag (rbs0 to rbs2) and the register set select flag (rss) in the psw. 2.3.2 short direct addressing short direct addressing which enables direct address specification by 1-byte data in an instruction work is applied to the fe20h to ff1fh space. the short direct memory is accessed as 8-bit or 16-bit data. when accessing the memory as 16- bit data, specification of even data for 1-byte address specify data will cause 2-byte data specified by continuous addresses of even and odd addresses to be accessed. (do not specify odd number for address specify data.) 2.3.3 special function register (sfr) addressing this addressing is applied to operations for the special function register (sfr) mapped in the sfr area of ff00h to ffffh. addressing is performed by 1-byte data in the instruction word corresponding to the lower 8 bits of the special function register address. for 16-bit access of 16-bit operational sfr, 2-byte data specified by continuous even and odd addresses is accessed as is the case with short direct addressing.
30 m pd78323, 78324 3. block functions 3.1 bus control unit (bcu) in the bcu, the necessary bus cycle is started according to the physical address obtained by the execution unit (exu). if no bus cycle startup request is made from the exu, a prefetch address is generated and instruction prefetch is carried out. the prefetched instruction code is fetched into the instruction queue. 3.2 execution unit (exu) in the exu, address calculation, arithmetic logical operation and data transfer are controlled by microprograms. a 256- byte ram is built in the exu. the 256-byte ram in the exu is accessible by the relevant instruction faster than peripheral ram (768 bytes). 3.3 rom/ram this block consists of a 32k-byte rom and a 768-byte ram. however, the m pd78323 does not incorporate rom. rom access can be disabled by ea pin. 3.4 interrupt controller various interrupt requests (nmi, intp0 to intp6) generated either externally or from the peripheral hardware are processed by the context switch, vectored interrupt or macro service function. the 3-level interrupt priority is also specified.
31 m pd78323, 78324 3.5 port functions table 3-1 lists the digital input/output ports. each port can carry out many control operations including 8 and other bit data input/output operations. table 3-1. port functions and features port name function feature remarks specifiable bit-wise for input/output. serves as rtp0 to rtp7 also specifiable for realtime output port. and pins. serves as nmi, intp0 to intp5, intp6/ti and pins. serves as t x d, r x d, port 3 5-bit input/output specifiable bit-wise for port pins or control pins. so/sb0, si/sb1, sck and pins. specifiable in 8-bit units for input or output. port 4 8-bit input/output functions as the multiplexed address/data bus (ad0 to CCCCCCCC ad7) in the external memory expansion mode. specifiable bit-wise for input or output. functions as the address bus (a8 to a15) in the external port 5 8-bit input/output memory expansion mode. CCCCCCCC pins which are not used as the address bus can be used as a port. input port pin. also functions as analog input to the serves as an0 to an7 a/d converter. and pins. functions as to00 to port 8 6-bit input/output specifiable bit-wise for the port pin or control pin. to03, to10 to to11 and pins. specifiable bit-wise for input/output. p90 and p91 function as rd output and wr output, port 9 4-bit input/output respectively, in the external memory expansion mode. CCCCCCCC p92 and p93 function as tas output and tmd output, respectively, in the high-speed fetch mode. port 2 8-bit input input port pin. functions as an external interrupt input. port 7 8-bit input port 0 8-bit input/outpput
32 m pd78323, 78324 3.6 clock generator the clock generator generates and controls internal system clocks (clk) supplied to the cpu. it is configured as shown in figure 3-1. figure 3-1. block diagram of clock generator x1 x2 stop mode f xx or f x 1/2 f clk internal system clock (clk) divider system clock generator remarks 1. f xx : crystal oscillator frequency 2. f x : external clock frequency 3. f clk : internal system clock frequency the system clock oscillator oscillates by a crystal resonator connected to x1 and x2 pins. it stops oscillating when set to the standby mode (stop). external clocks can be input to the system clock oscillator. in such cases, input a clock signal to the x1 pin and input the reverse phase of the clock signal to the x2 pin. the x2 pin can also be left open. caution when using external clocks, do not set the stbc stp bit. the divider generates internal system clocks (f clk ) by dividing a system clock oscillator output (fxx for crystal oscillation and fx for external clocks) into two parts.
33 m pd78323, 78324 figure 3-2. externally-mounted system clock generator (a) crystal oscillator cautions 1. when the system clock oscillator is used, the following points should be noted concerning wiring within broken lines shown in figure 3-2, in order to prevent the effects of wiring capacitance, etc. ? keep the wiring as short as possible. ? do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. ? ensure that oscillator capacitor connection points are always at the same potential as v ss . do not ground in a ground pattern in which a high current flows. ? do not take a signal from the oscillator. 2. when an external clock is input to the x1 pin and the x2 pin is left open, ensure that no loads such as wiring capacitance are connected to the x2 pin. (b) external clock (i) when the inverted phase of an external clock to be input to the x1 pin is input to the x2 pin (ii) when x2 pin is left open x2 x1 v ss pd78324 m x1 x2 external clock pd78324 m x1 x2 open external clock pd78324 m
34 m pd78323, 78324 3.7 realtime pulse unit (rpu) this unit can measure pulse intervals and frequencies, and generate programmable pulse outputs. it consists mainly of two timers. to flexibly cope with many applications, the configuration of registers connected to the timers can be changed using programs. to meet various applications, toggle output (6 max.) or set/ reset output (4 max.) can be selected as timer output. 3.7.1 configuration the realtime pulse unit is configured mainly of timer 0 (tm0) which functions as a 16-bit or 18-bit free running timer and timer 1 (tm1) which functions as a 16-bit timer/event counter shown in figure 3-3.
35 m pd78323, 78324 figure 3-3. realtime pulse unit configuration 16-bit timer/event counter tm1 (clear control) intp0 (opposite edge) ovf match intcm10 intcm11 match t r s t to11 to10 compare reg. cm10 compare reg. cm11 intp6/ti f clk /16 intov ovf intcm00 intcm01 intcm02 intcm03 intcc01 capture reg. ctx0 intp0 intp4 capture/compare reg. ccx0 match match mode1 mode0 intp0 intccx0 capture/compare reg. cc01 capture reg. ct03 capture reg. ct02 capture reg. ct01 intp5 intccx0 intp3 intp2 intp1 intp0 f clk /4 compare reg. cm03 compare reg. cm02 compare reg. cm01 compare reg. cm00 2 0 f clk /8 16/18-bit free running timer 10 11 15 17 tm0 t r s t r s t r s t to03 to02 to01 to00
36 m pd78323, 78324 3.7.2 realtime output function the realtime output port can set/reset port outputs bit-wise in synchronization with the trigger signal transmitted from the rpu (realtime pulse unit). it enables to generate multi-channel synchronous pulses easily. figure 3-4. realtime output port wr port wr rtpr rtpr n intcm03 r d s q p0 n output latch pmc0 n = 0 pmc0 n = 1 p0 n pm0 n = 1 pm0 n = 0 rd intccx0 rtps n wr rtps wr ptp internal bus rtp n
37 m pd78323, 78324 3.8 a/d converter the m pd78324 incorporates a high-speed, high-resolution 10-bit analog/digital (a/d) converter. this a/d converter is equipped with eight analog inputs (an0 to an7) and a/d conversion result register (adcr) which holds the conversion results. upon termination of conversion, the interrupt which can start the macro service is generated. figure 3-5. a/d converter block diagram 3.9 serial interface the m pd78324 is equipped with the following two independent channels for the serial interface function. asynchronous serial interface clock synchronous serial interface ? 3-wire serial i/o mode ? serial bus interface mode (sbi mode) since the m pd78324 incorporates a baud rate generator, it can set any serial transfer rate irrespective of the operating frequency. the baud rate generator functions for the 2-channel serial interface. the serial transfer rate can be selected from 75 bps to 19.2 kbps by setting the mode register. an0 an1 an2 an3 an4 an5 an6 an7 input circuit adm (8) internal bus 8 sample & hold circuit comparator sar (10) d/a converter adcr (10) 10 internal bus av ref av ss 10 10
38 m pd78323, 78324 figure 3-6. asynchronous serial interface block diagram brgm brg sck sl cl ps0 ps1 rex asim 2 1 match clear f clk /8 f clk /4 send/receive baud rate generator output baud rate generator selector 16 1 16 1 intsr receive control parity check shift register receive buffer r x d t x d rxb shift register ove fe pe asis txs send control parity addition internal bus intst intser
39 m pd78323, 78324 bsye ackd acke ackt cmdd reld cmdt relt 8 sbic set clear d so latch q busy/ acknowledge detector shift register sio internal bus mod0 cls0 cls1 mod1 wup crxe ctxe mod2 csim 8 si/sb1 so/sb0 n-ch open drain output enable sck bus release/ command/acknowledge detector serial clock counter serial clock controller interrupt signal generation controller intcsi mpx cls1 cls0 baud rate generator output f clk /8 f clk /32 figure 3-7. block diagram of clock synchronous serial interface
40 m pd78323, 78324 3.10 watchdog timer the watchdog timer is used to prevent program overrun and deadlock. normal operation of the program or system can be confirmed by checking that no watchdog timer interrupt has been generated. thus, an instruction to clear the watchdog timer (timer start) is set into each program module. if the watchdog timer clear instruction is not cleared within the time period set into the watchdog timer and the watchdog timer overflows, a watchdog timer interrupt is generated, and a low level is generated to wdto pin, thereby notifying of an error in the program. the watchdog timer can also be used to maintain the oscillation stabilizing time of the oscillator after the stop mode has been released. figure 3-8 shows the watchdog timer configuration. figure 3-8. watchdog timer configuration f clk /2 8 f clk /2 10 f clk /2 12 watchdog timer (8 bits) clear timer (5 bits) oscillation stabilizing time controller intwdt wdto wdt clr wdt stop overflow
41 m pd78323, 78324 4. interrupt functions 4.1 overview in the m pd78324, various interrupt requests generated externally or from the on-chip peripheral hardware are handled in the following three processing modes. interrupt requests are classified into the following three groups. ? nonmaskable interrupt requests ? maskable interrupt requests ? interrupt requests by software figure 4-1 shows the maskable interrupt request processing modes. table 4-1 gives a listing of interrupt factors which can be processed. figure 4-1. interrupt request processing modes handled by vectored interrupt processing interrupt request handled by context switching handled by macro service ? mk = 1 (interrupt masked) vectored interrupt and macro service reserved mk = 0 (interrupt unmasked) ism = 0 (vectored interrupt processing mode) di vectored interrupt processing reserved ei cse = 0 vectored interrupt processing executed cse = 1 context switching executed ism = 1 (macro service processing mode) macro service processing executed
42 m pd78323, 78324 table 4-1. list of interrupt factors available interrupt default interrupt factor generator macro vector table request type priority request signal function unit service address CCC CCC brk instruction CCC CCC 003eh CCC CCC operation code trap CCC CCC 003ch (external interrupt) CCC intwdt watchdog timer (wdt) CCC 0004h 0 intov timer 0 overflow (rpu) 0006h 1 intp0 intp0 pin input (external) 0008h 2 intp1 intp1 pin input (external) 000ah 3 intp2 intp2 pin input (external) 000ch 4 intp3 intp3 pin input (rpu/exteranl) 000eh 5 intp4/intccx0 intp4 pin input/ccx0 match signal (rpu/exteranl) 0010h 6 intp5/intcc01 intp5 pin input/cc01 match signal (rpu/exteranl) 0012h 7 intp6/ti intp6 pin input/ti input (exteranl) 0014h 8 intcm00 cm00 match signal (rpu) 0016h 9 intcm01 cm01 match signal (rpu) 0018h 10 intcm02 cm02 match signal (rpu) 001ah 11 intcm03 cm03 match signal (rpu) 001ch 12 intcm10 cm10 match signal (rpu) 001eh 13 intcm11 cm11 match signal (rpu) 0020h 14 intsr serial receive terminate interrupt (uart) 0024h 15 intst serial send terminate interrupt (uart) 0026h 16 intcsi serial send/receive interrupt (csi) 0028h 17 intad a/d conversion terminate interrupt (a/d) 002ah CCC CCC intser note serial receive error signal (uart) CCC CCC note reset CCC reset reset input CCC CCC 0000h note this is a test factor. a vectored interrupt is not generated. software non- maskable maskable nmi nmi pin input CCC 0002h CCC
43 m pd78323, 78324 4.2 macro service the macro service function is executed at the interrupt request to carry out data operation and data transfer in hardware terms between the special function register area and the memory space. upon startup of the macro service, the cpu stops program execution temporarily. 1-byte/2-byte data operation and transfer are automatically carried out between the special function register (sfr) and the memory. upon termination of the macro service, the interrupt request flag is reset to 0 and the cpu restarts program execution. when the cpu carries out the macro service operations as many as set into the macro service counter (msc), a vectored interrupt request is generated. figure 4-2. macro service processing sequence example ; data transfer, and realtime output port control macro service processing interrupt request generated macro service execution msc msc? msc = 0? yes no ism 0 next instruction executed interrupt request flag 0 ; macro service counter (msc) decrement (by 1) vectored interrupt request occurred
44 m pd78323, 78324 4.3 context switching function this is the function to first select the specified register bank in hardware terms by generating an interrupt request or executing brkcs instruction, to branch the selected register bank to the vector address prestored in the register bank, and also to stack the current pc and psw contents into the register bank. 4.3.1 context switching function at interrupt request the context switching function start is enabled by setting the cse bit preset at each interrupt request to 1. if an unmasked interrupt request for which the context switching function has been enabled is generated in the ei state, the register bank which is specified by the lower 3 bits of the lower address (even address) of the corresponding interrupt vector table address is selected. the vector address prestored in the selected register bank is transferred to the pc, the pc and psw contents are saved into the register bank, and the operation is branched to the interrupt processing routine. return is by means of executing the retcs instruction. figure 4-3. context switching at interrupt request register banks (0 to 7) rbank n pc psw exchange save a b r5 r7 d h x c r4 r6 e l vp up
45 m pd78323, 78324 4.3.2 context switching function by brkcs instruction the context switching function can be started by executing brkcs instruction. the context switched register bank is specified by the lower 3-bit immediate data of the 2nd operation code of brkcs instruction. when brkcs instruction is executed, the register bank specified by the 3-bit immediate data is selected, the vector address prestored in the register bank is set and branched to the pc, and the pc and psw contents are saved into the register bank. return is by means of executing the retcsb instruction. figure 4-4. context switching by execution of brkcs instruction op code op code n 2 n 1 n 0 000 111 rbank0 rbank7 register bank specification (brkcs) register banks (0 to 7) rbank n (n = 0 ?7) pc psw exchange save a b r5 r7 d h x c r4 r6 e l vp up
46 m pd78323, 78324 5. standby functions the m pd78324 has the standby function to decrease the power consumption of the system. the following two modes are available for execution of the standby function. ? halt mode........ mode for halting the cpu operation clock. the total power consumption of the system can be decreased by intermittent operation in combination with the normal operating mode. ? stop mode....... mode for stopping the whole system by stopping the oscillator. considerably low power consumption with leak current only can be set. each mode is set by the software. figure 5-1 shows standby mode (stop/halt mode) transition. figure 5-1. standby status transition normal status stop halt reset release halt set unmasked interrupt generated nmi stop set reset release
47 m pd78323, 78324 6. external device expansion function the m pd78324 can expand external devices (data memory, program memory peripheral device) for areas (8000h to faffh) except the internal rom and ram areas. table 6-1 and 6-2 show the pin used for external device access and the pin function setting procedure. table 6-1. pin function setting ( m pd78324) memory expansion mode register mm0 to mm2 mm7 fetch cycle control register 00h 00h except 00h ea pin 1 remarks 0 1 0 1 port mode expansion mode general port setting prohibited ad0 to ad7 rd wr external device connection mode m pd71p301 connection mode set to a8 to a15 in steps general port tas tmd pin function p40 to p47 p50 to p57 p90 p91 p92 p93 p50 to p57 pins according to the externally expanded memory size. the memory can be expanded in steps from 256 bytes to about 32k bytes. the pins which are not used as the address bus can be used as the general-purpose input/output port. table 6-2. port and address setting for port 5 ( m pd78324) p57 p56 p55 p54 p53 p52 p51 p50 external address space port port port port port port port port 256 bytes or less port port port port a11 a10 a9 a8 4k bytes or less port port a13 a12 a11 a10 a9 a8 16k bytes or less a15 a14 a13 a12 a11 a10 a9 a8 about 32k bytes or less table 6-3. pin function setting ( m pd78323) ad0 to ad7 a8 to a15 rd wr memory expansion mode register mm7 fetch cycle control register 00h except 00h ea pin astb 1 remarks CC 0 1 external device connection mode m pd71p301 connection mode general port tas tmd pin function ad0 to ad7 a8 to a15 rd wr p92 p93 m pd78324 emulation mode tas tmd
48 m pd78323, 78324 7. operation after reset if the reset input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status (reset status). if reset input becomes high level, program execution is started. initialize the contents of various registers in the program as required. change the number of cycles for the programmable wait register and the fetch cycle control register in particular. the reset input pin is equipped with an analog delay noise suppressor to prevent malfunctioning due to noise. cautions 1. while reset is active(low level), all pins remain high impedance (except wdto, av ref , av dd , av ss , v dd , v ss , x1 and x2). 2. if ram has been expanded externally, mount a pull-up resistor to the p90/rd and p91/wr pins. it is possible that the p90/rd and p91/wr pins become high impedance resulting in an external ram contents corruption or input unit damage. in addition, signals may collide on the address/data bus, resulting in the destruction of the input/output circuit. figure 7-1. reset signal acknowledge for reset operation upon power-up, secure the oscillation stabilizing time of about 40 msec from power-up to reset acknowledge as shown in figure 7-2. figure 7-2. reset upon power-up reset input analog delay removed as noise analog delay reset acknowl- edged analog delay reset release oscillation stabilizing time analog delay reset release v dd reset
49 m pd78323, 78324 8. instruction set this chapter covers instruction operations. for the operation codes and the number of instruction execution clock cycles, see m pd78322 users manual (ieu-1248) . (1) operand representation format and description method in each instruction operand column, enter the operand using the description method for the instruction operand representation format (refer to the assembler specification for details). if two or more factors are included in the descriptio n method column, select one factor. the capital alphabetic letters and +, -, #, $, ! and [ ] symbols are keywords and should be described as they are. in case of immediate data, describe appropriate numeric values or labels. when describing labels, make sure to describe #, $, ! and [ ] symbols. table 8-1. operand representation and description method r r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 r1 r0, r1, r2, r3, r4, r5, r6, r7 r2 c, b rp rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7 rp1 rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7 rp2 de, hl, vp, up sfr special function register code (see table 2-2 ) sfrp special function register code (16-bit operation enable register; see table 2-2 ) rp0, rp1, rp2, rp3, rp4, rp5/psw, rp6, rp7 post (two or more instructions can be described. only push and pop instructions can be described for rp5 and only pushu and popu instructions can be described for psw.) [de], [hl], [de+], [hl+], [de-], [hl-], [vp], [up] ; register indirect mode [de+a], [hl+a], [de+b], [hl+b], [vp+de], [vp+hl] ; based indexed mode [de+byte], [hl+byte], [vp+byte], [up+byte], [sp+byte] ; based mode word[a], word[b], word[de], word[hl] ; index mode saddr fe20h to ff1fh immediate data or label saddrp fe20h to ff1eh immediate data (bit0 = 0) or label (for 16-bit operation) $addr16 0000h to fdffh immediate data or label; relative addressing !addr16 0000h to fdffh immediate data or label; immediate addressing (up to ffffh describable by mov instruction) addr11 800h to fffh immediate data or label addr5 40h to 7eh immediate data (bit0 = 0) note or label word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label n 3-bit immediate data (0 to 7) note do not make work access to bit0 = 1 (odd address). remarks 1. although rp and rp1 have the same describable register names, they generate different codes. 2. r, r1, rp, rp1 and post can be described with absolute names (r0 to r15, rp0 to rp7) as well as functional names (x, a, c, b, e, d, l, h, ax, bc, de, hl, vp, up (refer to table 2-1 for details of the relationships between the absolute and functional names). 3. immediate addressing is enabled for all spaces. relative addressing is only enabled from the first address of the subsequent instruction to the range of C128 to +127. mem representation format description method
50 m pd78323, 78324 r1 byte (saddr) byte sfr byte r r1 a r1 a (saddr) (saddr) a (saddr) (saddr) a sfr sfr a a (mem) (mem) a a ((saddrp)) ((saddrp)) a a (addr16) (addr16) a psw l byte psw h byte psw l a psw h a a psw l a psw h a r1 r r1 a (mem) a (saddr) a sfr a ((saddrp)) (saddr) (saddr) mnemonic r1, #byte saddr, #byte sfr note , #byte r, r1 a, r1 a, saddr saddr, a saddr, saddr a, sfr sfr, a a, mem mem, a a, [saddrp] [saddrp], a a, !addr16 !addr16, a pswl, #byte pswh, #byte pswl, a pswh, a a, pswl a, pswh a, r1 r, r1 a, mem a, saddr a, sfr a, [saddrp] saddr, saddr 2 3 3 2 1 2 2 3 2 2 1-4 1-4 2 2 4 4 3 3 2 2 2 2 1 2 2-4 2 3 2 3 bytes operand operation flags s z ac p/v cy mov xch note if stbc and wdm are described for sft, a different dedicated instruction having a different number of bytes is used. remark for the symbols in the flags column, refer to the table below. instruction group 8-bit data transfer symbol description (blank) no change 0 clear to 0. 1 set to 1. set/clear according to the result. p p/v flag operates as a parity flag v p/v flag operates as an overflow flag. r the previously stored value is restored.
51 m pd78323, 78324 ax, sfrp sfrp, ax rp1, !addr16 !addr16, rp1 ax, mem mem, ax ax, saddrp ax, sfrp saddrp, saddrp rp,rp1 ax, mem a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr a, mem mem, a a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr a, mem mem, a movw xchw add addc mnemonic rp1, #word saddrp, #word sfrp, #word rp, rp1 ax, saddrp saddrp, ax saddrp, saddrp 3 4 4 2 2 2 3 2 2 4 4 2-4 2-4 2 3 3 2 2-4 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 bytes operation flags s z ac p/v cy operand rp1 word (saddrp) word sfrp word rp rp1 ax (saddrp) (saddrp) ax (saddrp) (saddrp) ax sfrp sfrp ax rp1 (addr16) (addr16) rp1 ax (mem) (mem) ax ax (saddrp) ax sfrp (saddrp) (saddrp) rp rp1 ax (mem) a, cy a + byte (saddr), cy (saddr) + byte sfr, cy sfr + byte r, cy r + r1 a, cy a + (saddr) a, cy a + sfr (saddr), cy (saddr) + (saddr) a, cy a + (mem) (mem), cy (mem) + a a, cy a + byte + cy (saddr), cy (saddr) + byte + cy sfr, cy sfr + byte + cy r, cy r + r1 + cy a, cy a + (saddr) + cy a, cy a + sfr + cy (saddr), cy (saddr) + (saddr) + cy a, cy a + (mem) + cy (mem), cy (mem) + a + cy v v v v v v v v v v v v v v v v v v instruction group 16-bit data transfer 8-bit opration
52 m pd78323, 78324 a, mem mem, a a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr a, mem mem, a a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr a, mem mem, a mnemonic a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 bytes operation flags s z ac p/v cy operand a, cy a C byte (saddr), cy (saddr) C byte sfr, cy sfr C byte r, cy r C r1 a, cy a C (saddr) a, cy a C sfr (saddr), cy (saddr) C (saddr) a, cy a C (mem) (mem), cy (mem) C a a, cy a C byte C cy (saddr), cy (saddr) C byte C cy sfr, cy sfr C byte C cy r, cy r C r1 C cy a, cy a C (saddr) C cy a, cy a C sfr C cy (saddr), cy (saddr) C (saddr) C cy a, cy a C (mem) C cy (mem), cy (mem) C a C cy a a ? byte (saddr) (saddr) ? byte sfr sfr ? byte r r ? r1 a a ? (saddr) a a ? sfr (saddr) (saddr) ? (saddr) a a ? (mem) (mem) (mem) ? a sub subc and v v v v v v v v v v v v v v v v v v p p p p p p p p p instruction group 8-bit opration
53 m pd78323, 78324 flags a, mem mem, a a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr a, mem mem, a a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr a, mem mem, a mnemonic a, #byte saddr, #byte sfr, #byte r, r1 a, saddr a, sfr saddr, saddr 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 bytes operation s z ac p/v cy operand a a M byte (saddr) (saddr) M byte sfr sfr M byte r r M r1 a a M (saddr) a a M sfr (saddr) (saddr) M (saddr) a a M (mem) (mem) (mem) M a a a M byte (saddr) (saddr) M byte sfr sfr M byte r r M r1 a a M (saddr) a a M sfr (saddr) (saddr) M (saddr) a a M (mem) (mem) (mem) M a a C byte (saddr) C byte sfr C byte r C r1 a C (saddr) a C sfr (saddr) C (saddr) a C (mem) (mem) C a or xor cmp p p p p p p p p p p p p p p p p p p v v v v v v v v v instruction group 8-bit opration
54 m pd78323, 78324 ax, #word saddrp, #word sfrp, #word rp, rp1 ax, saddrp ax, sfrp saddrp, saddrp ax, #word saddrp, #word sfrp, #word rp, rp1 ax, saddrp ax, sfrp saddrp, saddrp r1 r1 rp1 rp1 rp1 mnemonic ax, #word saddrp, #word sfrp, #word rp, rp1 ax, saddrp ax, sfrp saddrp, saddrp 3 4 5 2 2 3 3 3 4 5 2 2 3 3 3 4 5 2 2 3 3 2 2 2 2 2 bytes operation flags s z ac p/v cy operand ax, cy ax + word (saddrp), cy (saddrp) + word sfrp, cy sfrp + word rp, cy rp + rp1 ax, cy ax + (saddrp) ax, cy ax + sfrp (saddrp), cy (saddrp) + (saddrp) ax, cy ax C word (saddrp), cy (saddrp) C word sfrp, cy sfrp C word rp, cy rp C rp1 ax, cy ax C (saddrp) ax, cy ax C sfrp (saddrp), cy (saddrp) C (saddrp) ax C word (saddrp) C word sfrp C word rp C rp1 ax C (saddrp) ax C sfrp (saddrp) C (saddrp) ax a r1 ax(quotient), r1(remainder) ax r1 ax(higher 16 bits), rp1(lower 16 bits) ax rp1 axde(quotient), rp1(remainder) axde rp1 ax(higher 16 bits), rp1(lower 16 bits) ax rp1 v v v v v v v v v v v v v v v v v v v v v 16-bit opration instruction group signed multiplication multiplication/division addw subw cmpw mulu divum muluw divux mulw
55 m pd78323, 78324 r1 r1 + 1 (saddr) (saddr) + 1 r1 r1 C 1 (saddr) (saddr) C 1 rp2 rp2 + 1 (saddrp) (saddrp) + 1 rp2 rp2 C 1 (saddrp) (saddrp) C 1 (cy, r1 7 r1 0 , r1 mC1 r 1m ) n times (cy, r1 0 r1 7 , r1 m+1 r1 m ) n times (cy r1 0 , r1 7 cy, r1 mC1 r1 m ) n times (cy r1 7 , r1 0 cy, r1 m+1 r1 m ) n times (cy r1 0 , r1 7 0, r1 mC1 r1 m ) n times (cy r1 7 , r1 0 0, r1 m+1 r1 m ) n times (cy rp1 0 , rp1 15 0, rp1 mC1 rp1 m ) n times (cy rp1 15 , rp1 0 0, rp1 m+1 rp1 m ) n times a 3C0 (rp1) 3C0 , (rp1) 7C4 a 3C0 , (rp1) 3C0 (rp1) 7C4 a 3C0 (rp1) 7C4 , (rp1) 3C0 a 3C0 , (rp1) 7C4 (rp1) 3C0 decimal adjust accumulator when a 7 = 0, x a, a 00h when a 7 = 1, x a, a ffh flags saddrp r1, n r1, n r1, n r1, n r1, n r1, n rp1, n rp1, n [rp1] [rp1] mnemonic r1 saddr r1 saddr rp2 saddrp rp2 1 2 1 2 1 3 1 3 2 2 2 2 2 2 2 2 2 2 2 1 bytes operation s z ac p/v cy operand v v v v p p p p 0p 0p 0p 0p p inc dec incw decw ror rol rorc rolc shr shl shrw shlw ror4 rol4 adjba adjbs cvtbw instruction group increase/decrease shift-rotate bcd calibration data conversion
56 m pd78323, 78324 sfr. bit, cy a. bit, cy x. bit, cy pswh. bit, cy pswl. bit, cy cy, saddr. bit cy, /saddr. bit cy, sfr. bit cy, /sfr. bit cy, a. bit cy, /a. bit cy, x. bit cy, /x. bit cy, pswh. bit cy, /pswh. bit cy, pswl. bit cy, /pswl. bit cy, saddr. bit cy, /saddr. bit cy, sfr. bit cy, /sfr. bit cy, a. bit cy, /a. bit cy, x. bit cy, /x. bit cy, pswh. bit cy, /pswh. bit cy, pswl. bit cy, /pswl. bit mnemonic cy, saddr. bit cy, sfr. bit cy, a. bit cy, x. bit cy, pswh. bit cy, pswl. bit saddr. bit, cy 3 3 2 2 2 2 3 3 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 bytes operation flags s z ac p/v cy operand cy (saddr.bit) cy sfr.bit cy a.bit cy x.bit cy psw h .bit cy psw l .bit (saddr.bit) cy sfr.bit cy a.bit cy x.bit cy psw h .bit cy psw l .bit cy cy cy ? (saddr.bit) cy cy ? (saddr.bit) cy cy ? sfr.bit cy cy ? sfr.bit cy cy ? a.bit cy cy ? a.bit cy cy ? x.bit cy cy ? x.bit cy cy ? psw h .bit cy cy ? psw h .bit cy cy ? psw l .bit cy cy ? psw l .bit cy cy M (saddr.bit) cy cy M (saddr.bit) cy cy M sfr.bit cy cy M sfr.bit cy cy M a.bit cy cy M a.bit cy cy M x.bit cy cy M x.bit cy cy M psw h .bit cy cy M psw h .bit cy cy M psw l .bit cy cy M psw l .bit mov1 and1 or1 instruction group bit manipulation
57 m pd78323, 78324 sfr. bit a. bit x. bit pswh. bit pswl. bit saddr. bit sfr. bit a. bit x. bit pswh. bit pswl. bit saddr. bit sfr. bit a. bit x. bit pswh. bit pswl. bit cy cy cy mnemonic cy, saddr. bit cy, sfr. bit cy, a. bit cy, x. bit cy, pswh. bit cy, pswl. bit saddr. bit 3 3 2 2 2 2 2 3 2 2 2 2 2 3 2 2 2 2 3 3 2 2 2 2 1 1 1 bytes operation flags s z ac p/v cy operand cy cy M (saddr.bit) cy cy M sfr.bit cy cy M a.bit cy cy M x.bit cy cy M psw h .bit cy cy M psw l .bit (saddr.bit) 1 sfr.bit 1 a.bit 1 x.bit 1 psw h .bit 1 psw l .bit 1 (saddr.bit) 0 sfr.bit 0 a.bit 0 x.bit 0 psw h .bit 0 psw l .bit 0 (saddr.bit) (saddr.bit) sfr.bit sfr.bit a.bit a.bit x.bit x.bit psw h .bit psw h .bit psw l .bit psw l .bit cy 1 cy 0 cy cy 1 0 xor1 set1 clr1 not1 set1 clr1 not1 instruction group bit manipulation
58 m pd78323, 78324 flags mnemonic bytes operation s z ac p/v cy operand call callf callt call brk ret retb reti push pushu pop popu movw incw decw chkl chkla (spC1) (pc+3) h , (spC2) (pc+3) l , pc addr16, sp spC2 (spC1) (pc+2) h , (spC2) (pc+2) l , pc 15C11 00001, pc 10C0 addr11,sp spC2 (spC1) (pc+1) h , (spC2) (pc+1) l , pc h (tpf, 00000000, addr5+1), pc l (tpf, 00000000, addr5), sp spC2 (spC1) (pc+2) h , (spC2) (pc+2) l , pc h rp1 h , pc l rp1 l , sp spC2 (spC1) (pc+2) h , (spC2) (pc+2) l , pc h (rp1+1), pc l (rp1), sp spC2 (spC1) psw h , (spC2) psw l (spC3) (pc+1) h , (spC4) (pc+1) l , pc l (003eh), pc h (003fh), sp spC4 ie 0 pc l (sp), pc h (sp+1), sp sp+2 pc l (sp), pc h (sp+1) psw l (sp+2), psw h (sp+3) sp sp+4 pc l (sp), pc h (sp+1) psw l (sp+2), psw h (sp+3) sp sp+4 (spC1) sfr h (spC2) sfr l sp spC2 {(spC1) post h , (spC2) post l ,sp spC2} n times note (spC1) psw h , (spC2) psw l , sp spC2 {(upC1) post h , (upC2) post l , up upC2} n times note sfr l (sp) sfr h (sp+1) sp sp+2 {post l (sp), post h (sp+1), sp sp+2} n times note psw l (sp), psw h (sp+1), sp sp+2 {post l (up), post h (up+1), up up+2} n times note sp word sp ax ax sp sp sp+1 sp spC1 (pin level) M (signal level before output buffer) a (pin level) M (signal level before output buffer) !addr16 !addr11 [addr5] rp1 [rp1] sfrp post psw post sfrp post psw post sp, #word sp, ax ax, sp sp sp sfr sfr note n indicates the number of registers described as post. 3 2 1 2 2 1 1 1 1 3 2 1 2 3 2 1 2 4 2 2 2 2 3 3 rrrrr rrrrr rrrrr p p instruction group stack manipulation call-return special
59 m pd78323, 78324 mnemonic !addr16 rp1 [rp1] $ addr16 $ addr16 3 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 3 3 3 3 4 4 3 3 3 3 bytes operation flags s z ac p/v cy operand pc addr16 pc h rp1 h , pc l rp1 l pc h (rp1+1), pc l (rp1) pc pc+2+jdisp8 pc pc+2+jdisp8 if cy=1 pc pc+2+jdisp8 if cy=0 pc pc+2+jdisp8 if z=1 pc pc+2+jdisp8 if z=0 pc pc+2+jdisp8 if p/v=1 pc pc+2+jdisp8 if p/v=0 pc pc+2+jdisp8 if s=1 pc pc+2+jdisp8 if s=0 pc pc+3+jdisp8 if (p/v M s) M z=0 pc pc+3+jdisp8 if p/v M s=0 pc pc+3+jdisp8 if p/v M s=1 pc pc+3+jdisp8 if (p/v M s) M z=1 pc pc+3+jdisp8 if z M cy=0 pc pc+3+jdisp8 if z M cy=1 pc pc+3+jdisp8 if (saddr.bit)=1 pc pc+4+jdisp8 if sfr.bit=1 pc pc+3+jdisp8 if a.bit=1 pc pc+3+jdisp8 if x.bit=1 pc pc+3+jdisp8 if psw h .bit=1 pc pc+3+jdisp8 if psw l .bit=1 pc pc+4+jdisp8 if (saddr.bit)=0 pc pc+4+jdisp8 if sfr.bit=0 pc pc+3+jdisp8 if a.bit=0 pc pc+3+jdisp8 if x.bit=0 pc pc+3+jdisp8 if psw h .bit=0 pc pc+3+jdisp8 if psw l .bit=0 br bc bl bnc bnl bz be bnz bne bv bpe bnv bpo bn bp bgt bge blt ble bh bnh bt bf $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 $ addr16 saddr. bit, $ addr16 sfr. bit, $ addr16 a. bit, $ addr16 x. bit, $ addr16 pswh. bit, $ addr16 pswl. bit, $ addr16 saddr. bit, $ addr16 sfr. bit, $ addr16 a. bit, $ addr16 x. bit, $ addr16 pswh. bit, $ addr16 pswl. bit, $ addr16 instruction group unconditional branch conditional branch
60 m pd78323, 78324 mnemonic bytes operation flags s z ac p/v cy operand pc pc+4+jdisp8 if (saddr.bit)=1 then reset (saddr.bit) pc pc+4+jdisp8 if sfr.bit=1 then reset sfr.bit pc pc+3+jdisp8 if a.bit=1 then reset a.bit pc pc+3+jdisp8 if x.bit=1 then reset x.bit pc pc+3+jdisp8 if psw h .bit=1 then reset psw h .bit pc pc+3+jdisp8 if psw l .bit=1 then reset psw l .bit pc pc+4+jdisp8 if (saddr.bit)=0 then set (saddr.bit) pc pc+4+jdisp8 if sfr.bit=0 then set sfr.bit pc pc+3+jdisp8 if a.bit=0 then set a.bit pc pc+3+jdisp8 if x.bit=0 then set x.bit pc pc+3+jdisp8 if psw h .bit=0 then set psw h .bit pc pc+3+jdisp8 if psw l .bit=0 then set psw l .bit r2 r2C1, then pc pc+2+jdisp8 if r2 0 (saddr) (saddr)C1, then pc pc+3+jdisp8 if (saddr) 0 pc h r5, pc l r4, r7 psw h , r6 psw l , rbs2C0 n, rss 0, ie 0 pc h r5, pc l r4, r5, r4 addr16, psw h r7, psw l r6 pc h r5, pc l r4, r5, r4 addr16, psw h r7, psw l r6 x.bit, $ addr16 pswh.bit, $ addr16 pswl.bit, $ addr16 saddr.bit, $ addr16 sfr.bit, $ addr16 a.bit, $ addr16 x.bit, $ addr16 pswh.bit, $ addr16 pswl.bit, $ addr16 r2, $ addr16 saddr, $ addr16 rbn !addr16 !addr16 saddr.bit, $ addr16 sfr.bit, $ addr16 a.bit, $ addr16 btclr bfset dbnz brkcs retcs retcsb 4 4 3 3 3 3 4 4 3 3 3 3 2 3 2 3 4 rrrrr rrrrr instruction group conditional branch context switching
61 m pd78323, 78324 mnemonic bytes operation flags s z ac p/v cy operand (de + ) a, c cC1 end if c=0 (de C ) a, c cC1 end if c=0 (de + ) (hl + ), c cC1 end if c=0 (de C ) (hl C ), c cC1 end if c=0 (de + ) a, c cC1 end if c=0 (de C ) a, c cC1 end if c=0 (de + ) (hl + ), c cC1 end if c=0 (de C ) (hl C ), c cC1 end if c=0 (de + ) C a, c cC1 end if c=0 or z=0 (de C ) C a, c cC1 end if c=0 or z=0 (de + ) C (hl + ), c cC1 end if c=0 or z=0 (de C ) C (hl C ), c cC1 end if c=0 or z=0 (de + ) C a, c cC1 end if c=0 or z=1 (de C ) C a, c cC1 end if c=0 or z=1 (de + ) C (hl + ), c cC1 end if c=0 or z=1 (de C ) C (hl C ), c cC1 end if c=0 or z=1 (de + ) C a, c cC1 end if c=0 or cy=0 (de C ) C a, c cC1 end if c=0 or cy=0 [de C ], [hl C ] [de + ], a [de C ], a [de + ], [hl + ] [de C ], [hl C ] [de + ], a [de C ], a [de + ], [hl + ] [de C ], [hl C ] [de + ], a [de C ], a [de + ], [hl + ] [de C ], [hl C ] [de + ], a [de C ], a [de + ], a [de C ], a [de + ], [hl + ] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movm movbk xchm xchbk cmpme cmpbke cmpmne cmpbkne cmpmc v v v v v v v v v v instruction group string
62 m pd78323, 78324 mnemonic bytes operation flags s z ac p/v cy operand (de + ) C (hl + ), c cC1 end if c=0 or cy=0 (de C ) C (hl C ), c cC1 end if c=0 or cy=0 (de + ) C a, c cC1 end if c=0 or cy=1 (de C ) C a, c cC1 end if c=0 or cy=1 (de + ) C (hl + ), c cC1 end if c=0 or cy=1 (de C ) C (hl C ), c cC1 end if c=0 or cy=1 stbc byte note wdm byte note rss rss rbs2 C 0 n, rss 0 rbs2 C 0 n, rss 1 no operation ie 1 (enable interrupt) ie 0 (disable interrupt) [de C ], a [de + ], [hl + ] [de C ], [hl C ] stbc, #byte wdm, #byte rbn rbn, alt [de + ], [hl + ] [de C ], [hl C ] [de + ], a 2 2 2 2 2 2 4 4 1 2 2 1 1 1 cmpbkc cmpmnc cmpbknc mov swrs sel nop ei di v v v v v v note if the operation code of stbc register and wdm register operation instructions is abnormal, an operation code trap interrupt is generated. operation in the eent of trap: (spC1) psw h , (spC2) psw l , (spC3) (pcC4) h , (spC4) (pcC4) l , pc l (003ch), pc h (003dh), sp spC4, ie 0 instruction group string cpu control
63 m pd78323, 78324 9. electrical specifications absolute maximum ratings (t a = 25 c) i ol i oh v ian v v av ref av dd > v dd v dd av dd av dd > v dd v dd av dd notes 1. except the pin described in note 2 . 2. p70/ani0 to p77/ani7 pins caution if the absoute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. in other words, the product may be physically damaged if any of the absolute maximum raings is exceeded. be sure to use the product without exceeding these rarings. recommended operating condition oscillation frequency t a v dd 8 mhz f xx 16 mhz C10 to +70 c +5.0 v 10 % capacitance (t a = 25 c, v ss = v dd = 0 v) parameter symbol test conditions rating unit v dd C0.5 to + 7.0 v av dd C0.5 to v dd + 0.5 v av ss C0.5 to + 0.5 v v i note 1 C0.5 to v dd + 0.5 v v o C0.5 to v dd + 0.5 v all output pins 4.0 ma all output pins total 90 ma all output pins C1.0 ma all output pins total C20 ma C0.5 to v dd + 0.5 C0.5 to av dd + 0.5 C0.5 to v dd + 0.3 C0.5 to av dd + 0.3 t a C10 to + 70 c t stg C65 to + 150 c note 2 supply voltage voltage input voltage output voltage output current low output current high analog input voltage a/d converter reference input voltage operating ambient temperature storage temperature typ. max. 10 20 20 unit pf pf pf min. parameter input capacitance output capacitance i/o capacitance test conditions symbol c i c o c io f=1 mhz unmeasured pins returned to 0 v.
64 m pd78323, 78324 oscillator characteristics (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) parameter oscillation frequency (f xx ) x1 input frequency (f x ) x1 input rise/fall time (t xr , t xf ) x1 input high/low level width (t wxh , t wxl ) min. 8 8 0 25 unit mhz mhz ns ns max. 16 16 20 80 recommended circuit or x1 x2 hcmos invertor resonator ceramic resonator or crystal resonator external clock x1 x2 hcmos invertor open x1 x2 c1 c2 v ss caution when using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. ? make the wiring as short as possible. ? avoid intersecting other signal conductors. avoid approaching lines in which very high fluctuating currents run. ? make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as v ss . avoid grounding with a grand pattern in which very high currents run. ? do not fetch signals from the oscillation circuit.
65 m pd78323, 78324 recommended oscillator constant ceramic resonator manufacturer product name frequency [mhz] c1 [pf] c2 [pf] csa8.00mt csa12.0mt csa14.74mxz040 csa16.00mxz040 8.0 12.0 14.74 16.0 30 30 15 15 cst8.00mtw cst12.0mtw cst14.74mxw0c3 cst16.00mxw0c3 8.0 12.0 17.74 16.0 on-chip on-chip murata mfg. co., ltd. crystal resonator manufacturer product name frequency [mhz] c1 [pf] c2 [pf] hc49/u-s hc49/u 10 10 kinseki co., ltd. 8 to 16 recommended constant recommended constant
66 m pd78323, 78324 dc characteristics (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol test conditions min. typ. max. unit v il 0 0.8 v v ih1 note 1 2.2 v ih2 note 2 0.8v dd v ol i ol = 2.0 ma 0.45 v v oh i oh = C400 m av dd C 1.0 v i li 0 v v i v dd 10 m a i lo 0 v v o v dd 10 m a i dd1 operating mode 40 75 ma i dd2 halt mode 20 45 ma v dddr stop mode 2.5 v v dddr = 2.5 v 2 10 m a v dddr = 5.0 v 10 % 10 50 m a input voltage low output voltage low output voltage high input leakage current v output leakage current v dd supply current data retention voltage data retention current stop mode i dddr input voltage high notes 1. except the pin descried in note 2 . 2. reset, x1, x2, p20/nmi, p21/intp0, p22/intp1, p23/intp2,p24/intp3, p25/intp4, p26/intp5, p27/ intp6/ti, p32/so/sb0, p33/si/sb1, p34/sck pins.
67 m pd78323, 78324 ac characteristics (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) non-consecutive read/write operation (with general-purpose memory connected) parameter symbol test conditions min. max. unit system clock cycle time t cyk 125 250 ns address setup time (vs. astb ? )t sast 32 ns address hold time (vs. astb ? )t hsta 32 ns rd ? delay time from address t dar 85 ns address float time from rd ? t fra 10 ns data input time from address t daid 222 ns data input time from rd ? t drid 112 ns rd ? delay time from astb ? t dstr 42 ns data hold time (vs. rd )t hrid 0ns address active time from rd t dra 50 ns rd low-level width t wrl 147 ns astb high-level width t wsth 37 ns wr ? delay time from address t daw 85 ns data output time from astb ? t dstod 102 ns data output time from wr ? t dwod 40 ns wr ? delay time from astb ? t dstw 42 ns data setup time (vs. wr )t sodw 147 ns data hold time (vs. wr )t hwod 32 ns astb delay time from wr t dwst 42 ns wr low-level width t wwl 147 ns
68 m pd78323, 78324 t cyk dependent bus timing definition parameter expression min./max. unit t sast 0.5t C 30 min. ns t hsta 0.5t C 30 min. ns t dar t C 40 min. ns t daid (2.5 + n) t C 90 max. ns t drid (1.5 + n) t C 75 max. ns t dstr 0.5t C 20 min. ns t dra 0.5t C 12 min. ns t wrl (1.5 + n) t C 40 min. ns t wsth 0.5t C 25 min. ns t daw t C 40 min. ns t dstod 0.5t + 40 max. ns t dstw 0.5t C 20 min. ns t sodw 1.5t C 40 min. ns t hwod 0.5t C 30 min. ns t dwst 0.5t C 20 min. ns t wwl (1.5 + n) t C 40 min. ns remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. n indicates the number of wait cycles defined by user software. 3. depends on t cyk for the bus timing shown in this table only.
69 m pd78323, 78324 serial operation (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v) parameter symbol test conditions min. max. unit sck output internal division by 8 1 m s sck input external clock 1 m s sck output internal division by 8 420 ns sck input external clock 420 ns sck output internal division by 8 420 ns sck input external clock 420 ns si setup time (to sck )t srxsk 80 ns si hold time (from sck )t hskrx 80 ns so delay time from sck ? t dsktx r = 1 k w , c = 100 pf 210 ns serial clock cycle time serial clock low-level width serial clock high-level width t cysk t wskl t wskh parameter symbol test conditions min. max. unit nmi high/low-level width t wnih ,t wnil 5 m s intp0 high/low-level width t wi0h ,t wi0l 8t t cyk intp1 high/low-level width t wi1h ,t wi1l 8t t cyk intp2 high/low-evel width t wi2h ,t wi2l 8t t cyk ntp3 high/low-level width t wi3h ,t wi3l 8t t cyk ntp4 high/low-level width t wi4h ,t wi4l 8t t cyk intp5 high/low-level width t wi5h ,t wi5l 8t t cyk intp6 high/low-level width t wi6h ,t wi6l 8t t cyk reset high/low-level width t wrsh ,t wrsl 5 m s ti high/low-level width t wtih ,t wtil in tm1 event counter mode 8t t cyk other operation (t a = C10 to +70 c, v dd = +5 v 10 %, v ss = 0 v)
70 m pd78323, 78324 a/d converter characteristics(t a = C10 to +70 c, v dd = +5 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd ) parameter symbol test conditions min. typ. max. unit resolution 10 bit total error note 1 4.5 v av ref av dd 0.4 % %fsr 3.4 v av ref av dd 0.7 %fsr quantization error 1/2 lsb conversion time t conv 144 t cyk sampling time t samp 24 t cyk zero scale error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref av dd 1.5 4.5 lsb full scale error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref av dd 1.5 4.5 lsb non-linear error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref av dd 1.5 4.5 lsb analog input voltage note 2 v ian C0.3 av dd v reference voltage av ref 3.4 av dd v av ref current ai ref 1.0 3.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data av ddr = 2.5 v 2.0 10 m a retention current av ddr = 5 v 10 % 10 50 m a stop mode ai ddr notes 1. quantization error excluded. 2. when C0.3 v v ian 0 v, the conversion result becomes 000h. when 0 v < v ian < av ref , the conversion is performed at a resolution of 10 bits. when av ref v ian av dd , the conversion result is 3ffh.
71 m pd78323, 78324 non-consecutive read operation non-consecutive write operation higher address higher address (clk) p50-p57 (output) p40-p47 (input/ output) astb (output) wr (output) lower address (output) undefined data (output) lower address (output) t wsth t sast t hwod t hsta t dstod t dwst t dstw t daw t dwod t sodw t wwl t sast t daid t wsth t dstr t hsta t hrid t dar t drid t wrl t fra t cyk hi-z hi-z hi-z hi-z t dra higher address higher address data (input) lower address (output) lower address (output) (clk) p50-p57 (output) p40-p47 (input/ output) astb (output) rd (output)
72 m pd78323, 78324 serial operation interrupt input timing t wskl t cysk t wskh t dsktx t srxsk t hskrx sck so si 0.8v dd 0.8v t wnih t wnil t winh t winl nmi intpn remarks n = 0 to 6
73 m pd78323, 78324 reset input timing ti pin input timing t wrsh t wrsl 0.8v dd 0.8v reset t wtih t wtil ti
74 m pd78323, 78324 10. package drawings 74 pin plastic qfp ( 20) item millimeters inches f 1 f 2 i 2.0 1.0 0.20 q 0.079 0.039 0.008 s74gj-100-5bj-3 note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. c 20.0?.2 0.787 m 0.15 0.006 0.1?.1 0.004?.004 +0.004 ?.003 +0.009 ?.008 a 23.2?.4 0.913 h 0.40?.10 0.016 +0.004 ?.005 l 0.8?.2 0.031 +0.009 ?.008 n 0.10 0.004 p 3.7 0.146 s 4.0 max. 0.158 max. +0.10 ?.05 b 20.0?.2 0.787 +0.009 ?.008 +0.017 ?.016 j 1.0 (t.p.) 0.039 (t.p.) r5 ? 5 ? d 23.2?.4 0.913 +0.017 ?.016 g 1 g 2 2.0 1.0 0.079 0.039 k 1.6?.2 0.063?.008 a b g 1 h ij c d p n k l m detail of lead end m 56 57 37 74 1 19 18 38 f 2 f 1 g 2 s q r
75 m pd78323, 78324 p68l-50a1-2 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. +0.007 ?.006 a b c d e f g h i j k m n p q t u 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 min. 3.4 1.27 (t.p.) 0.40 1.0 0.12 23.12 0.20 0.15 r 0.8 0.20 +0.10 ?.05 0.992 0.008 0.953 0.953 0.992 0.008 0.076 0.024 0.173 0.110 0.035 min. 0.134 0.050 (t.p.) 0.016 0.005 0.910 0.006 r 0.031 0.008 +0.009 ?.008 +0.009 ?.008 +0.004 ?.005 +0.004 ?.002 +0.009 ?.008 n k m q a u 68 b d c 1 f e t p m g h ij 68 pin plastic qfj ( 950 mil)
76 m pd78323, 78324 11. recommended soldering conditions the m pd78323 and 78324 should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mount- ing technology manual (ie1-1207) . for soldering methods and conditions other than those recommended below, contact our salesman. table 11-1. soldering conditions for surface mount type m pd78323gj-5bj : 74-pin plastic qfp (20 20 mm) m pd78324gj- -5bj : 74-pin plastic qfp (20 20 mm) soldering method soldering conditions package peak temperature: 230 c, time: 30 sec. max. (at 210 c or above) infrared reflow number of times: once, time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) package peak temperature: 215 c, time: 40 sec. max. (at 200 c or above) vps number of times: once, time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) pin temperature: 300 c max, time: 3 sec. max. (per side of the device) recommended condition symbol soldering method soldering conditions package peak temperature: 235 c, time: 30 sec. max. (at 210 c or above) number of times: twice or less, time limit: 7 days note (thereafter 36 hours prebaking required at 125 ?c) (1) the second reflow should be started after the temperature of the device which would have been changed by the first reflow has returned to normal. (2) please avoid flux water washing after the first reflow. package peak temperature: 215 c, time: 40 sec. max. (at 200 c or above), number of times: twice or less, time limit: 7 days note (thereafter 36 hours prebaking required at 125 ?c) (1) the second reflow should be started after the temperature of the device which would have been changed by the first reflow has returned to normal. (2) please avoid flux water washing after the first reflow. pin temperature: 300 c max., time: 3 sec. max. (per side of the device)) recommended condition symbol infrared reflow ir30-367-2 vp15-367-2 m pd78323lp : 68-pin plastic qfj ( 950 mil) m pd78324lp- : 68-pin plastic qfj ( 950 mil) pin part heating ir30-107-1 vp15-107-1 vps note for the storage period after dry-pack decompression, storage conditions are max. 25 c, 65 % rh. caution use more than one soldering method should be avoided (except in the case of pin part heating). pin part heating
77 m pd78323, 78324 m pd78324 m pd78323 m pd78322 m pd78320 m pd78312a m pd78310a 111 96 250 ns (at 16 mhz operation) 500 ns (at 12 mhz operation) 32768 8 bits CC 16384 8 bits CC 8192 8 bits CC 1024 8 bits 640 8 bits 256 8 bits 64k bytes 16 (including 8 analog inputs) 12 (including 4 analog inputs) CC 1 39 21 39 21 40 24 real-time pulse unit multi-function pulse i/o unit ? 18/16-bit free running timer 1 ? 16-bit presettable up-/down-counter ? 16-bit timer/event counter 1 2 ? 16-bit compare register 6 ? 16-bit free running counter capture ? 18-bit capture register 4 function 2 ? 18-bit capture/compare register 2 ? 16-bit interval timer 2 ? real-time output port 8 ? high-precision pwm output 2 ? real-time output port : 4 bits 2 count unit mode 4 (4-multiplication mode) function available counter start function by interval timer external trigger available ? dedicated on-chip baud rate generator ? 8 bits (full-duplex transmission/ ? uart ...1 channel reception) ? sbi ? dedicated on-chip baud rate generator ? 3-wire serial i/o ? 2 transfer modes (asynchronous mode, i/o interface mode) eight 10-bit resolution inputs four 8-bit resolution inputs ? 8 external, 14 internal (shared with external 2) ? 4 external, 13 internal ? 3-level programmable priority order ? 8-level programmable priority order ? 3 processing methods (vectored interrupt, context switching and macro service functions) ...1 channel internal memory appendix a. list of 78k/iii series products (1/2) basic instruction minimum instruction execution time rom ram memory space input i/o lines output i/o pulse unit serial communication interface a/d converter interrupt real-time pulse unit ? 18/16-bit free running timer 1 ? 16-bit timer/event counter 1 ? 16-bit compare register 6 ? 18-bit capture register 4 ? 18-bit capture/compare register 2 ? real-time output port 8
78 m pd78323, 78324 instruction set others package instructions for m pd78312 and 78310 significantly increased. list of 78k/iii series products (2/2) test source m pd78324 m pd78323 m pd78322 m pd78320 m pd78312a m pd78310a internal : 1 following instructions added for m pd78312 and 78310 ? movw rp1, !addr16 instruction ? movw !addr16, rp1 instruction ? on-chip watchdog timer ? standby function (stop/halt) ? 20-bit time base counter ? pseudo static ram refresh function ? 64-pin plastic shurink dip (750 mil) ? 68-pin plastic qfj ( 950 mil) ? 64-pin plastic qfp (14 20 mm) ? 74-pin plastic qfp (20 20 mm) ? 64-pin plastic quip ? 68-pin plastic qfj ( 950 mil) ? 68-pin plastic qfj ( 950 mil) ? 74-pin plastic qfp (20 20 mm) ? 80-pin plastic qfp (14 20 mm)
79 m pd78323, 78324 appendix b. tools b.1 development tools the following development tools are available for system development using the m pd78324. language processor 78k/iii series relocatable assembler (ra78k/iii) 78k/iii series c compiler (cc78k/iii) refers to the relocatable assembler which can be used commonly for the 78k/iii series. equipped with the macro function, the relocatable assembler is aimed at improved development efficiency. the assembler is also accompanied by the structured assembler which can describe the program control structure explicitly, thus making it possible to improve the productivity and the maintainability of the program. host machine pc-9800 series ibm pc/at tm and its compatible machine hp9000 series 700 tm sparcstation tm news tm supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc dat cartridge tape (qic-24) part number m s5a13ra78k3 m s5a10ra78k3 m s7b13ra78k3 m s7b10ra78k3 m s3p16ra78k3 m s3k15ra78k3 m s3r15ra78k3 os ms-dos tm pc dos tm hp-ux tm sunos tm news-os tm part number m s5a13cc78k3 m s5a10cc78k3 m s7b13cc78k3 m s7b10cc78k3 m s3p16cc78k3 m s3k15cc78k3 m s3r15cc78k3 host machine pc-9800 series ibm pc/at and its compatible machine hp9000 series 700 sparcstation news supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc dat cartridge tape (qic-24) os ms-dos pc dos hp-ux sunos news-os refers to the c compiler which can be commonly used in the 78k/iii series. this compiler is a program converting the programs written in the c language to those object codes which are executable by microcontrollers. when using this compiler, the 78k/iii series relocatable assembler (ra78k/iii) is required. remark relocatable assembler and c compiler operations are assured only on the host machine and the os above.
80 m pd78323, 78324 prom writing tools this prom programmer allows programming, in standalone mode or via operation from a host computer, of a singlechip microcontroller with on-chip prom by connection of the board provided and a separately available programmer adapter. it can program typical 256k-bit to 4m-bit proms. prom programmer made by data i/o japan corporation. prom programmer adapters for writing programs to the m pd78p324 with a general prom programmer such as the pg-1500. pa-78p324gj ... for m pd78p324gj pa-78p324kc ... for m pd78p324kc pa-78p324kd ... for m pd78p324kd pa-78p324lp ... for m pd78p324lp ordering code (product name) supply medium os host machine connects pg-1500 and host machine via a serial and parallel interface, and controls the pg-1500 on the host machine. unisite 2900 pg-1500 controller software hardware pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 5-inch 2hd m s5a10pg1500 ibm pc/at and its pc dos 3.5-inch 2hc m s7b13pg1500 compatible machine 5-inch 2hc m s7b10pg1500 remark operation of the pg-1500 controller is guaranteed only on the host machines and operating systems quoted above. pg-1500 pa-78p324gj pa-78p324kc pa-78p324kd pa-78p324lp
81 m pd78323, 78324 debugging tools these are the in-circuit emulators which can be used for the development and debugging of application systems. debugging is performed by connecting them to a host machine. the ie-78327-r can be used commonly for both the m pd78322 subseries and the m pd78328 subseries. the ie-78320-r can be used for the m pd78322 subseries. these are the emulation probes for connecting the ie-78327-r or ie-78320-r to a target system. ep-78320gj-r: for 74-pin plastic qfp ep-78320l-r: for 68-pin plastic qfj this program is for controlling the ie-78327-r from a host machine. it can execute commands automatically, thus enabling more efficient debugging. hardware software host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13ie78327 m s5a10ie78327 m s7b13ie78327 m s7b10ie78327 os ms-dos pc dos this program is for controlling the ie-78320-r from a host machine. it can execute commands automatically, thus enabling more efficient debugging. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc part number m s5a13ie78320 m s5a10ie78320 m s7b10ie78320 os ms-dos pc dos remarks 1. the operation of each software is assured only on the host machine and the os above. 2. m pd78322 subseries: m pd78320, 78322, 78p322, 78323, 78324, 78p324, 78320(a), 78320(a1), 78320(a2), 78322(a), 78322(a1), 78322(a2), 78323(a), 78323(a1), 78323(a2), 78324(a), 78324(a1), 78324(a2), 78p324(a), 78p324(a1), 78p324(a2) m pd78328 subseries: m pd78327, 78328, 78p328, 78327(a), 78328(a) note the existing product ie-78320-r is a maintenance product. if you are going to newly purchase an in-circuit emulator, please use the alternative product ie-78327-r. ie-78327-r ie-78320-r note ep-78320gj-r ep-78320l-r ie-78327-r control program (ie controller) ie-78320-r control program note (ie controller)
82 m pd78323, 78324 development tool configurations note the socket is supplied with the emulation probe. remarks 1. it is also possible to use the host machine and the pg-1500 by connecting them directly by the rs-232-c. 2. in the diagram above, representative software supply media and 3.5-inch fds. host machine pc-9800 series ibm pc/at or its compatible machine software relocatable assembler (with structured assembler) pg-1500 controller ie controller pd78p324gj pd78p324lp pd78p324kd pd78p324kc pa-78p324gj pa-78p324lp pa-78p324kc pa-78p324kd +++ programmer adapters prom-incorporated products rs-232-c ie-78327-r in-circuit emulator rs-232-c pg-1500 prom programmer emulation probes socket for connecting the emulation probe and the target system ep-78320gj-r ep-78320l-r ev-9200g-74 socket for plastic qfj target system m m m m note
83 m pd78323, 78324 b.2 evaluation tools to evaluate the functions of the m pd78324, the following tools are made available. part number eb-78320-98 eb-78320-pc function by connecting to a host machine, it is possible to evaluate the functions equipped by the m pd78324 in a simple manner. the command system of this product basically conforms to that of ie-78327-r and ie-78320-r. therefore, it is easy to move to the development work of application systems by ie-78327-r or ie- 78320-r. in addition a turbo access manager ( m pd71p301) note can be mounted on the board. host machine pc-9800 series ibm pc/at or its compatible machine real-time os (rx78k/iii) the rx78k/iii is designed to provide a multi-task environment in the field of control application where real-time operation is required. by using this real-time os, the performance of the whole system can be improved by allocating cpus idle time to other processings. the rx78k/iii provides the system call based on the m itron specifications. the rx78k/iii package provides tools (configurators) for creating rx78k/iiis nucleus and multiple information table. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13rx78320 m s5a10rx78320 m s7b13rx78320 m s7b10rx78320 os ms-dos pc dos caution to purchase the operating system above, you need to fill in a purchase application form beforehand and sign a contract allowing you to use the software. remark when using the real-time os rx78k/iii, you need the assembler package ra78k/iii (optional) as well. note the turbo access manager ( m pd71p301) is a maintenance product. cautions 1. this product is not a development tool of m pd78324 application systems. 2. this product is not equipped with the emulation function for executing the rom incorporated in the m pd78324. b.3 embedded software the following embedded software programs are available to perform program development and maintenance more efficiently. eeal-time os
84 m pd78323, 78324 fuzzy knowledge data creation tools (fe9000, fe9200) translator (ft78k3) note fuzzy inference module (fi78k/iii) note fuzzy inference debugger (fd78k/iii) this program supports inputting/editing/evaluating (through simulation) of the fuzzy knowledge data (fuzzy rules and membership functions). fuzzy inference development support system host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13fe9000 m s5a10fe9000 m s7b13fe9200 m s7b10fe9200 os ms-dos pc dos winsows tm this program converts the fuzzy knowledge data obtained with fuzzy knowledge data creation tools to an assembler source program for ra78k/iii. host machine pc-9800 series ibm pc/at and its compatible machine supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13ft78k3 m s5a10ft78k3 m s7b13ft78k3 m s7b10ft78k3 os ms-dos pc dos supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13fi78k3 m s5a10fi78k3 m s7b13fi78k3 m s7b10fi78k3 os ms-dos pc dos supply medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc part number m s5a13fd78k3 m s5a10fd78k3 m s7b13fd78k3 m s7b10fd78k3 os ms-dos pc dos host machine pc-9800 series ibm pc/at and its compatible machine this program executes fuzzy inference. fuzzy inference is executed by being linked to the fuzzy knowledge data converted by the translator. this is a support software program for evaluating and adjusting the fuzzy knowledge data at a hardware level by using the in-circuit emulator. host machine pc-9800 series iibm pc/at and its compatible machine note under development
85 m pd78323, 78324 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 license not needed : m pd78323 the customer must judge the need for license : m pd78324 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m pd78323, 78324

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